(a) Field of the Invention
The present invention relates to a method for forming a Cu (copper) interconnection structure for a semiconductor device on a substrate, and more in particular to a method for forming a minute multilevel interconnection structure of copper having a low electric resistance.
(b) Description of the Related Art
A conventional and standard process of forming an interconnection structure in a semiconductor device includes forming a first level interconnect by processing a first level interconnect layer made of Al or an Al alloy by means of photolithography and etching, depositing an interlayer dielectric film on the first level interconnect, flattening the first level interconnect, forming a via hole, filling the via hole with tungsten, depositing a second level interconnect layer made of Al or an Al alloy and processing the second level interconnect layer by means of photolithography and etching.
In the conventional interconnection process, the process becomes complicated with the progress of the multi-level interconnection structure because of the increase of the number of steps of the photolithography and the etching. Further, the filling of a space between interconnects without forming a void is difficult because the coverage of the interlevel dielectric film becomes severe with the miniaturization of the pitch of the interconnects.
In the generation in which the line width is between 0.18 and 0.20 micronmeter, the line pitch becomes narrow and the increase of the capacitance between the interconnects is not negligible so that the performance deterioration of LSI may be caused due to the signal/propagation delay. As one possible way of preventing this deterioration, a copper interconnect having a lower electric resistance compared with the Al or the Al alloy attracts attention. However, the etching of copper is difficult to be controlled, and as a result, the processing of copper to make an interconnect in accordance with a process similar to that employed for making the conventional Al interconnect is hardly practicable.
In order to overcome this disadvantage, a method for forming a multi-level interconnection structure having a copper interconnect in accordance with the Damasin process is attracting attention.
The above method for forming the multi-level structure having the copper interconnect will be described referring to FIG. 1.
At first, as shown in FIG. 1A, a SiO.sub.2 film 14 made of BPSG (boro-phospho silicate glass) is formed on a silicon substrate 12, and then a via-hole (not shown) is formed for exposing a diffused region (source/drain region) in the silicon substrate 12 to form a conductive plug (not shown) such as a tungsten plug in electric contact with the diffused region of the silicon substrate 12.
Then, as shown in FIG. 1B, a plasma SiO.sub.2 film 16 is formed on the SiO.sub.2 film 14 employing a plasma CVD (chemical vapor deposition) method. Reaction gases such as silan (SiH.sub.4) and O.sub.2 are employed for forming the plasma SiO.sub.2 film 16.
After the formation of a photoresist film 18 on the plasma SiO.sub.2 film 16, a mask to which an interconnect pattern is transferred by patterning is formed by employing photolithography and etching. Then, by employing the mask 18 as an etching mask, etching is performed to form an interconnect trench 20 which penetrates the plasma SiO.sub.2 film 16 to expose a conductive plug (not shown) formed in the SiO.sub.2 film 14 as shown in FIG. 1C.
The mask 18 is removed by oxygen plasma ashing. Then, as shown in FIG. 1D, a TiN film 22 is deposited as a barrier layer on the whole surface of the substrate, and further a copper layer 24 is formed on the TiN film 22 to fill the interconnect trench 20 with the copper.
The copper layer 24 and the TiN film 22 are polished by means of CMP (chemical mechanical polishing) until the plasma SiO.sub.2 film 16 is exposed, and as shown in FIG. 1E, the first level copper interconnect (copper layer) 24 is formed which electrically contacts with the conductive plug (not shown) at the bottom and has an exposed top surface and side surfaces contacting with the SiO.sub.2 film 16.
Then, a SiO.sub.2 film 26 made of such as BPSG acting as an interlevel dielectric film is formed on the wafer surface, and a photoresist film is formed thereon followed by patterning thereof to obtain a mask 28. As shown in FIG. 1F, the SiO.sub.2 film 26 is etched using the above mask 28 as an etching mask to form a via-hole 30 for exposing the first level copper interconnect 24.
In order to reduce a contact resistance between a tungsten plug to be embedded in the via-hole 30 and the first level copper interconnect 24, the wafer is washed for cleaning the bottom of the via-hole 30 or the surface of the first level copper interconnect 24.
After the washing, the substrate is thermally treated or receives a baking treatment at a temperature range between 300 and 700.degree. C. to remove liquid containing moisture entering into the interlayer dielectric film from the substrate during the washing so as to elevate an electromigration durability by promoting satisfactory crystallization of the first level copper interconnect 24. During the thermal treatment, the first level copper interconnect 24 is exposed through the via-hole 30.
Then, as shown in FIG. 1G, a TiN film 32 acting as a barrier layer is formed on the whole surface of the substrate, and a tungsten layer 34 is formed on the TiN film 32.
The TiN film 32 and the tungsten layer 34 are then polished by means of CMP until the plasma SiO.sub.2 film 26 is exposed, and as shown in FIG. 1H, the tungsten plug 34 embedded in the via-hole 30 is formed.
Further, a plasma SiO.sub.2 film 38 is formed on the plasma SiO.sub.2 film 26, and an interconnect trench is formed similarly to the formation of the first level copper interconnect 24. Then, a TiN film 40 and a copper layer 42 are formed, and this laminate layer is polished by CMP to make a second level copper interconnect as shown in FIG. 1I.
A thermal treatment is conducted thereon under a hydrogen atmosphere at a temperature of about 400.degree. C. (hydrogen annealing) to promote the proper crystallization of the first level copper interconnect 24 and the second level copper interconnect 42. As a result, the crystal grains become larger to elevate the electromigration durability.
In the conventional method of forming the copper interconnect in accordance with the Damasin process, the electric resistances of the first level copper interconnect and the second level copper interconnect and those of contact portions between the tungsten plug and the first level copper interconnect and between the former and the second level copper interconnect inevitably increase.
This is a restriction for miniaturization of an interconnect and realization of a multi-level structure, and is a bar to high integration of a semiconductor device.
Although, in the above description, a problem about an electric resistance increase has been pointed out by taking the copper interconnect formation by means of the Damasin process as an example, this problem arises not only in the Damasin process but also in a conventional process consisting of depositing a copper layer, forming a copper interconnect by means of patterning, embedding an dielectric film and opening a via-hole.